Scan testing is a well established technique for checking the interconnections of integrated circuits, as well as for checking the functionality and performance of logic circuits. IEEE Standard 1149.1-1990 defines circuitry for scan testing.
A simple scan test is intended to check integrity of connections in an integrated circuit. This is achieved by feeding a scan chain of test information through the connections and ensuring that the correct information is scanned out.
However, certain blocks within integrated circuit devices do not lend themselves to full scan testing. For instance a memory device such as a RAM has data, address, and control inputs, and data output. However the data output is not directly linked to the data, address and control inputs. Thus in a scan test such a memory device is normally provided with circuitry such that the data input to the memory device can be bypassed directly to its data output. In this way the data input and output connections of the memory device can be scan tested, but there is no means for scan testing the control and address inputs of the memory device. The data input to the memory device will have the same width as the data output and therefore can be readily fed directly onto its memory data output in a scan test.
In such arrangements, the memory device itself is not tested during a scan test, but is tested in a separate built-in self-test (BIST). For this purpose a BIST controller is usually provided which generates test signals for the memory device on the data input, address and control signal lines, and checks that the correct data outputs are generated by the memory device. Specifically the BIST controller may write into the memory device particular bits of test patterns, and then read the test patterns to ensure that the test patterns read are those as written.
Thus there is a deficiency in the testing of integrated circuits including such memory devices, in that the although the memory device itself can be properly tested using a built in self-test, and the data input and data output connections can be tested using a scan test, there is no means for specifically testing the integrity of the connections of the control and address signal lines.
This deficiency in applying scan testing to integrated circuits is associated not only with addressed memory devices but also is associated generally with devices having a number of inputs greater than the number of outputs and in which there is no direct correlation between the inputs and the outputs. Such other devices, may include, for example a FIFO queue, or a stack that does not take an address but instead has an internal state to cope with addressing.